In recent years, miniaturization of semiconductor devices has led to a reduction in the line width of circuit patterns. Thus, there has been an increasing reduction in the distance between an active area serving as a diffusion layer and a channel and another adjacent active area. As a result, the withstand voltage between an active area in which a contact section is formed and another adjacent active area has been decreasing.
Thus, it has been difficult to form a semiconductor device with an appropriate withstand voltage between an active area in which a contact section is formed and another adjacent active area.
A related technique has been proposed in which a void portion is formed between adjacent floating gates and/or between adjacent control gates (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-302950). However, this technique is used for adjacent memory cell transistors. Hence, this technique fails to increase the withstand voltage between an active area in which a contact section is formed and another adjacent active area.